The present invention relates to a semiconductor device for use as a switching element.
Recently, the needs of semiconductor switches such as analog switches, semiconductor relays and the like are increasing for use as switches for turning high frequency signals on or off. To use these semiconductor switches for turning on or off high frequency signals, they are required to have linear current-voltage characteristics (having no offset voltage) and low on-state resistance and also to have a small output capacitance in the signal-OFF state so as to improve the high frequency cut-off characteristics.
SOI (silicon-on-insulator)-LDMOSFET (lateral double-diffused MOSFET) is known as a semiconductor element capable of meeting these requirements.
A conventional SOI-LDMOSFET is constructed as follows, using a SOI substrate which comprises a semiconductor substrate (1) formed from a single crystal silicon, an insulating layer (2) formed from a silicon oxide on the semiconductor substrate (1), and a semiconductor layer (3) formed from a single crystal silicon on the insulating layer (2) (see FIG. 10A)).
As shown in FIG. 10A, in this SOI-LDMOSFET, a p+-type well region (5) and an n++-type drain region (4) are formed with a space therebetween in the n-type semiconductor layer (3), and an n++-type source region (6) is further formed in the p+-type well region (5). In this regard, a part of the p+-type well region (5) and the n-type semiconductor layer (3) are located between the n++-type source region (6) and the n++-type drain region (4).
In addition, a gate electrode (9) is formed from, for example, a poly-silicon, which is disposed on a gate-insulating layer (8) formed on the p+-type well region (5) between the n++-type source region (6) and the n++-type drain region (4). The gate electrode (9) is formed overhanging the n++-type source region (6) and the drift region located between the p+-type well region (5) and the n++-type drain region (4) in the n-type semiconductor layer (3), respectively, taken into account margins for a shift of the position in the process of production.
A source electrode (11) and a drain electrode (10) are formed on the n++-type source region (6) and the n++-type drain region (4), respectively.
In the conventional SOI-LDMOSFET constructed above as shown in FIG. 10A, while a voltage is being applied across the n++-type source region (6) and the n++-type drain region (4) through the source electrode (11) and the drain electrode (10), not less than a predetermined voltage is being applied to the gate electrode (9), so that a channel is formed, under strong inversion condition, in a part of the p+-type well region (5) under the gate electrode (9), and that current flows between the n++-type source region (6) and the n++-type drain region (4) through the channel (the state of ON).
When the voltage to the gate electrode is decreased, the p+-type well region (5) turns into the original p-type Layer, so that a PN junction in reverse bias is formed between the p+-type well region and the n++-type drain region (4). As a result, current does not flow between the n++-type source region (6) and the n++-type drain region (4).
In the SOI-LDMOSFET shown in FIG. 10A, a part of the n-type semiconductor layer (3) between the p+-type well region (5) forming the channel and the n++-type drain region (4) is called a drift region (20), and the impurity concentration NO of the drift region (20) is so selected as to satisfy the RESURF condition expressed by the following equation (1).
Tsoixc3x97NO≈1xc3x971012 (atm/cm2)xe2x80x83xe2x80x83(1) 
wherein Tsoi represents the thickness of the drift region.
As described above, the conventional SOI-LDMOSFET achieves high withstand voltage by selecting the impurity concentration NO of the drift region (20) so that the above RESURF condition for providing optimal conditions relative to a surface electric field can be satisfied. In this regard, in the SOI-LDMOSFET shown in FIG. 10A, the impurity concentration NO of the drift region (20) is so selected as to be uniform over a whole of the drift region (20).
Lately, structures for further improving the withstand voltage of the SOI-LDMOSFET shown in FIG. 10A are proposed in U.S. Pat. Nos. 5,300,448, 5,412,241 and so on.
In the SOI-LDMOSFET disclosed in U.S. Pat. No. 5,300,448, the n-type drift region (50) locates between the drain region (52) having the drain electrode (56) formed thereon and the source region (51) having the source electrode (54) formed thereon as shown in FIG. 11, and the drift region (50) is so formed that the impurity concentration of the drift region (50) can linearly decrease as the distance from the drain region (52) increases. In addition, a space between the source region (51) and the drift region (50) has a gate electrode (59) formed therein spaced by the gate oxide layer (58) and a p-type base region (60) for forming a channel. Constructed as above, the SOI-LDMOSFET disclosed in U.S. Pat. No. 5,300,448 succeeds in uniforming the surface and the internal electric field of the drift region (50) and thus further improving the withstand voltage.
However, the SOI-LDMOSFET disclosed in U.S. Pat. No. 5,300,448 has a problem in that it is impossible to decrease the length of the drift region (50) (the length along which current flows). This disadvantage comes from the following structure: as shown in FIG. 12, the drift region is formed on the semiconductor layer (3) through a mask having a plurality of openings (40) which are formed so that the distance between each of the openings changes in order and such a semiconductor layer (3) is doped with a predetermined amount of impurity and then treated by heating, so that the impurity concentration of the drift region (50) changes in order. This structure makes it hard to shorten the length of the drift region (50). It is described in U.S. Pat. No. 5,300,448 that the length of the drift region (50) is 40 to 50 xcexcm
Therefore, on-state resistance becomes higher because the length of the drift region (50) is long in the SOI-LDMOSFET disclosed in U.S. Pat. No. 5,300,448.
The SOI-LDMOSFET proposed in U.S. Pat. No. 5,300,448 has a further problem in that it is inevitably needed to decrease the thickness of the drift region (50) in order to improve the withstand voltage, which leads to poor heat release. This results in a problem that allowable current in the state of ON can not be increased.
The SOI-LDMOSFET proposed in U.S. Pat. No. 5,412,241 or the like provides the structure which makes it possible to decrease the on-state resistance and to improve the withstand voltage characteristics. However, this SOI-LDMOSFET has a gate-field plate structure and therefore has a problem in that the output capacitance is large.
In the meantime, the switch for turning a high frequency signal on or off is keenly demanded in the voltage class from 20 to 300 V. In case where a SOI-LDMOS of this class is constructed so as to have an ideal structural parameter, it is estimated that the optimal value of the length of the drift region is 1 to 15 xcexcm. However, it is hard to form a drift region having an optimal length of 1 to 15 xcexcm, because the method of producing the SOI-LDMOSFET disclosed in U.S. Pat. No. 5,300,448 has a problem in the processing precision.
The present invention is made to overcome the foregoing problems, and the first object of the present invention is to provide a semiconductor device capable of increasing allowable current in the state of ON while ensuring the demanded withstand voltage and decreasing output capacitance and on-state resistance.
The second object of the invention is to provide a process for readily producing the same semiconductor device with high accuracy.
A semiconductor device according to the present invention comprising a semiconductor layer formed on a semiconductor substrate, and the semiconductor layer includes
a first conductivity type-drain region formed in a part of the semiconductor layer,
a second conductivity type-well region formed in a part of the semiconductor layer and apart from the drain region,
a first conductivity type-source region formed in the well region and apart from one end of the well region on the side of the drain region,
a first conductivity type-drift region formed between one end of the well region and the drain region and in contact with both the well region and the drain region, the impurity concentration of said drift region decreasing both in the lateral direction and in the vertical direction as the distance from the drain region increases, the lateral direction being parallel to the surface of the semiconductor layer, the vertical direction being perpendicular to the surface of the semiconductor layer,
a gate oxide layer formed on the well region located between the drift region and the source region, and
a gate electrode formed on the gate oxide layer.
Constructed above, a depletion layer is effectively spread in a part of the drift region in contact with the well region, so that the concentration of an electric field can be prevented and that high withstand voltage can be achieved. Further, since the semiconductor layer can be formed with a relative large thickness, the thermal resistance can be decreased, and thus, the allowable current in the state of ON can be increased.
Further, in the semiconductor device according to the present invention, it is preferable that the semiconductor layer is formed on an insulating layer on the semiconductor substrate.
Further, it is preferable that the impurity concentration in the lateral direction of the drift region changes obeying the Gaussian distribution having, as a parameter, the distane x from the drain region in the lateral direction, and that the impurity concentration in the vertical direction of the drift region changes obeying the Gaussian distribution having, as a parameter, the distance y from the drain region in the vertical direction.
By doing so, the impurity concentration distribution in the drift region can be controlled by the diffusion from the side of the drain region in the course of constructing the semiconductor device, so that the semiconductor device can be readily formed with high accuracy.
Further, a semiconductor device capable of having withstand voltage of 20 to 300 V class which is widely demanded for switches for turning high frequency signals on or off, and having a drift length of about 1 to about 15 xcexcm can be easily constructed.
Further, it is preferable that the gate electrode is formed so as to overhang the drift region as if covering a part of the drift region, and that the impurity concentration of the part of the drift region locating just under the gate electrode is lower than the impurity concentration N(RESURF) which satisfies the RESURF condition.
Thus, the on-state resistance can be held lower, and the output capacitance can be effectively decreased.
Further, it is preferable that the impurity concentration of a part of the drift region in the vicinity of the drain region is higher than the impurity concentration N(RESURF) which satisfies the RESURF condition Thus, the on-state resistance can be decreased.
In this regard, the RESURF condition referred to herein is to satisfy the following equation.
Tsoixc3x97N(RESURF)≈1xc3x971012 (atm/cm2) 
Tsoi: the thickness of the semiconductor layer (cm)
N(RESURF): the impurity concentration (atm/cm3) satisfying the RESURF condition
Further, it is preferable that the thickness t of the semiconductor layer is set within a rang of 0.3 xcexcmxe2x89xa6txe2x89xa615 xcexcm.
By selecting the thickness t of the semiconductor layer so as to satisfy the requirement of 0.5 xcexcmxe2x89xa6txe2x89xa64 xcexcm, the resultant semiconductor device as a switching element can have withstand voltage of 25 to 100 V class and show excellent high frequency wave characteristics.
Further, by selecting the thickness t of the semiconductor layer so as to satisfy the requirement of 0.5 xcexcmxe2x89xa6txe2x89xa61.5 xcexcm, the resultant semiconductor device as a switching element can have withstand voltage of 25 to 50 V class and show excellent high frequency wave characteristics.
Further, it is preferable that the lateral distance of the drift region from one end of the drain region to one end of the well region is set 15 xcexcm or less. By doing so, the on-state resistance can be decreased. Further, by doing so, the impurity concentration distribution can be formed in practical time by the diffusion from the side of the drain region.
Another aspect of the present invention relates to a process for constructing a semiconductor device comprising a semiconductor layer formed on a semiconductor substrate, and the process comprises the steps of separately forming a first conductivity type-drain region and a first conductivity type-source region apart from each other, forming a drift region between the drain region and the source region and in contact with the drain region, and forming a channel region in contact with the source region. The process of the present invention is characterized by comprising the steps of doping a region for forming the drain region with a first conductivity type-impurity, and heating and diffusing the impurity in the drift region.
According to the process of the present invention, there can be formed such a drift region that the impurity concentration in the lateral direction changes obeying the Gaussian distribution using, as a parameter, the distance x from the drain region in the lateral direction, and that the impurity concentration in the vertical direction changes obeying the Gaussian distribution using, as a parameter, the distance y from the drain region in the vertical direction.
Further, according to the process of the present invention, the introduction of the impurity into the drain region and the introduction of the impurity into the drift region can be carried out, using the same mask window, so that the semiconductor device can be readily constructed easilly with high accuracy.